Galaxy Technology Empire

Huang Junjie did not pay attention to the desperate struggles of Shin-Etsu and LG Chem.

Because for Galaxy Technology, the area of ​​silicon wafers has lost its meaning.

If necessary, Neutron Star can produce large-area square wafers at any time, so even if Shin-Etsu and LG Chem develop 18-inch round wafers, it will not help.

Neutron Star Materials' square wafers are ahead of round wafers in all aspects, which is an unstoppable trend. Their desperate struggle is nothing more than a mantis trying to control the car.

Huang Haojie is now in the Semiconductor Research Institute of Galaxy Technology.

Galaxy Technology itself has recruited more than a hundred semiconductor graduates, plus five engineers or researchers poached from domestic semiconductor companies, plus a dozen engineers and researchers brought over by Zhang Rujing.

Although Galaxy Technology's Semiconductor Research Institute currently has only over a hundred people, it is small but has all the internal organs.

Huang Junjie looked at the orderly Semiconductor Research Institute and nodded with satisfaction.

"Li Xiang, how are you studying the mechanism of C31 transporting other chip materials?"

Li Xiang raised his glasses and replied with excitement: "This C31 fullerene can transport most of the raw materials for making chips. Even if the other small parts cannot be transported, we can also use transportable raw materials to replace them."

"very good."

"Boss, I think this invention of yours can win the Explosives Award." A Mediterranean researcher marveled.

"So what about the Dynamite Award? I don't need this kind of thing." Huang Junjie is not from a real academic background, so he doesn't pay much attention to things like the Dynamite Award.

... All the researchers and engineers were speechless and choked. Others were trying hard to get the dynamite award, but my boss didn't care at all.

Huang Haojie and a group of engineers are developing a chip manufacturing process that is different from the current chip process.

Generally speaking, chip manufacturers purchase silicon wafers directly from silicon wafer factories instead of producing them themselves.

The chip manufacturing plant will first check the silicon wafer. After checking that there is no damage, it can be put into the production line. There may be various film-forming processes in the early stage, and then it will enter the process of applying photoresist.

Lithography process is a pattern printing technology and a key process in the integrated circuit manufacturing process.

First, the photoresist (photosensitive resin) is dropped on the silicon wafer, and is evenly spread into a photoresist film by high-speed rotation, and an appropriate temperature is applied to cure the photoresist film.

Photoresist is a material that is very sensitive to light, temperature, and humidity. Its chemical properties can change after exposure to light. This is the basis of the entire process.

Next is UV exposure.

As far as a single technology process is concerned, the photolithography process is the most complex and the most expensive.

Because the photolithography template, lens, and light source jointly determine the size of the transistor "printed" on the photoresist.

Put the silicon wafer coated with photoresist into the exposure device of the stepper and repeat exposure machine to "copy" the mask pattern.

There is a pre-designed circuit pattern in the mask. After ultraviolet rays pass through the mask and are refracted by a special lens, the circuit pattern in the mask is formed on the photoresist layer.

Generally speaking, the circuit pattern obtained on the silicon wafer is 1/10, 1/5, and 1/4 of the pattern on the mask, so the step-and-repeat exposure machine is also called a "reduction projection exposure device."

There are two major factors that determine the performance of a stepper and repeat exposure machine: one is the wavelength of light, and the other is the numerical aperture of the lens.

If you want to reduce the size of transistors on silicon wafers, you need to find shorter wavelength light (EUV, extreme ultraviolet) that can be reasonably used and lenses with larger numerical apertures (there are limits due to the lens material).

Dissolve part of the photoresist and develop the exposed silicon wafer.

Taking positive photoresist as an example, after spraying a strong alkaline developer, the photoresist irradiated by ultraviolet light will undergo a chemical reaction. Under the action of the alkaline solution, a chemical reaction will occur and dissolve in the developer, while the photoresist that has not been exposed will The photoresist pattern will be intact.

After development, the surface of the silicon wafer needs to be rinsed and sent to an oven for heat treatment to evaporate the water and cure the photoresist.

Then enter the etching stage.

Immersing the silicon wafer in a special etching tank containing etching chemicals can dissolve the exposed parts of the silicon wafer, while the remaining photoresist protects the parts that do not need to be etched.

During this period, ultrasonic vibration is applied to accelerate the removal of impurities attached to the surface of the silicon wafer and prevent etching products from staying on the surface of the silicon wafer causing uneven etching.

The next step is to remove the photoresist.

The photoresist is ashed by oxygen plasma to remove all photoresist.

At this point, the first layer of designed circuit patterns can be completed.

Repeat steps 6-8. Since the current transistor has been designed with 3D FinFET, it is impossible to produce the required pattern at one time. You need to repeat steps 6-8 for processing. There will also be various film-forming processes (insulation) in the middle. film, metal film) are involved to obtain the final 3D transistor.

Next is the ion implantation stage.

The process of intentionally introducing specific impurities into a specific area is called "impurity diffusion."

In addition to controlling the conductivity type (P junction, N junction) through impurity diffusion, it can also be used to control the impurity concentration and distribution.

Nowadays, the ion implantation method is generally used for impurity diffusion. In the ion implanter, the conductive impurities to be doped are introduced into the arc chamber and ionized through discharge. After being accelerated by the electric field, the ions with energy of tens to thousands of keV are The beam is injected from the surface of the silicon wafer.

After ion implantation, the silicon wafer needs to undergo heat treatment. On the one hand, the principle of thermal diffusion is used to further "press" the impurities into the silicon. On the other hand, the integrity of the crystal lattice is restored and the electrical properties of the impurities are activated.

The ion implantation method has the advantages of low processing temperature, uniform and large-area implantation of impurities, and easy control. Therefore, it has become an indispensable process in very large-scale integrated circuits.

Remove the photoresist again. After the ion implantation is completed, the photoresist mask remaining from the selective doping can be removed.

At this time, a small portion of the silicon atoms inside the single crystal silicon have been replaced with "impurity" elements, thereby generating free electrons or holes.

Insulating layer processing: At this time, the prototype of the transistor has been basically completed. Using the vapor deposition method, a layer of silicon oxide film is fully deposited on the surface of the silicon wafer to form an insulating layer.

Photolithography mask technology is also used to open holes in the interlayer insulating film to lead out conductor electrodes.

Precipitate a copper layer, use sputtering deposition method to deposit a copper layer for wiring on the entire surface of the silicon wafer, and continue to use photolithography mask technology to carve the copper layer to form the source, drain, and gate of the field effect transistor.

Finally, an insulating layer is deposited over the entire silicon wafer surface to protect the transistors.

Construct a circuit connecting transistors.

After a long process, billions of transistors have been produced.

All that remains is the question of how to connect these transistors.

In the same way, a layer of copper is formed first, followed by fine operations such as photolithography masking and etching openings, and then the next layer of copper is deposited.

This process is repeated several times, depending on the transistor size of the chip and the degree of replication.

The result is an extremely complex network of multi-layer connected circuits.

Since IC now contains various refined components and huge interconnected circuits, the structure is very complex. The actual number of circuit layers has reached as high as 30 layers. The surface has more and more uneven surfaces, with great differences in height. Therefore, CMP chemical machinery was developed. Polishing technology.

CMP grinding is performed after each layer of circuit is completed.

In addition, in order to successfully complete multi-layer Cu three-dimensional wiring, a new wiring method of Damascus method was developed. After plating the barrier metal layer, the Cu film is sputtered as a whole, and then CMP is used to remove the Cu and barrier metal layer outside the wiring to form Required wiring.

The chip circuit has been basically completed at this point. It has gone through hundreds of different processes, all of which are based on fine operations. Any error in any place will cause the entire silicon wafer to be scrapped. On a silicon wafer of more than 100 square millimeters, several One billion transistors are the culmination of all the wisdom of humankind since civilization began.

To make it so complicated, hundreds of processes are just to carve lines on the silicon wafer and inject conductive impurities to form a switch.